Blog – Page 2 – Jerico

What Is Driving the Shift to Lead-Free HASL and Fast PCB Prototyping? For most hardware teams targeting Europe or North America, staying on traditional Sn‑Pb HASL finishes is no longer a safe default. Regulatory pressure from RoHS and REACH, together with customer factory audits, is pushing even relatively simple products toward lead-free surface finishes as…

For engineers and project managers pushing the boundaries of miniaturization and performance with HDI (High-Density Interconnect) PCBs, the gap between a flawless CAD model and a reliable, manufacturable board is wider than ever. The complexity of microvias, sequential lamination, and mixed-material stackups means that traditional “design-then-verify” approaches are a direct path to budget overruns and…

For hardware engineers and product managers, the relentless drive for smaller, lighter, and more powerful devices creates a fundamental design paradox: how to pack more functionality into less space without compromising performance, signal integrity, or thermal management. The traditional two-dimensional PCB approach hits an absolute wall. This article explores how multi-layer PCB technology—and its advanced…

For power design engineers pushing the limits in electric vehicles, server racks, or industrial drives, a common and costly assumption persists: to carry more current, simply widen the copper trace. However, when currents surpass the 10A threshold, this approach not only fails but can actively undermine reliability. This article moves beyond basic IPC-2152 charts to…

Every high-speed digital or RF engineer has experienced this frustration: your PCB stackup calculator shows perfect 50Ω impedance, but the physical board measures 42Ω or 58Ω. This gap between calculation and reality isn’t just a minor discrepancy—it’s a direct threat to signal integrity, system performance, and project timelines. The problem isn’t your calculator; it’s the…