In PCB design, the humble via and plated through hole (PTH) are foundational elements, yet their misapplication is a leading cause of field failures, thermal issues, and signal degradation. While often used interchangeably, PTHs and vias serve distinct electrical, mechanical, and thermal purposes. Confusing them leads to inefficient designs, inflated costs, and compromised reliability. This guide, grounded in 25 years of Jerico’s manufacturing expertise, provides a definitive comparison. We move beyond basic definitions to explore how advanced via technologies—from filled vias for high-current applications to microvias for HDI—are critical for solving modern challenges in power electronics, automotive systems, and high-speed communications.
The Critical Distinction: Plated Through Hole (PTH) vs. Via
Understanding the core functional difference between a PTH and a via is the first step toward Design for Manufacturing (DFM) excellence. The choice impacts everything from assembly yield to long-term reliability.
| Feature | Plated Through Hole (PTH) | Via (Through-Via, Blind, Buried) | Practical Design Implication |
|---|---|---|---|
| Primary Function | Component Mounting & Electrical Connection. Designed to mechanically secure and electrically connect through-hole technology (THT) components like connectors, large capacitors, or power devices. | Interlayer Electrical Connection Only. Solely provides a conductive path between different layers of the PCB. Never used for component leads. | Using a via to mount a component will fail. The annular ring is not designed for mechanical stress, and solder wicking can create open circuits. Always specify PTHs for THT parts in your CAD library. |
| Typical Size & Aspect Ratio | Larger diameter (e.g., 0.8mm – 2.0mm). Aspect ratio (board thickness/hole diameter) typically kept below 8:1 for reliable plating. | Smaller diameter (e.g., 0.2mm – 0.5mm for through-vias). Microvias can be ≤0.1mm. Aspect ratios for through-vias are also kept manageable, while microvias have very low aspect ratios. | PTHs consume more real estate. Misusing a large PTH where a small via would suffice wastes valuable routing space, especially in dense designs, pushing layer count and cost up unnecessarily. |
| Manufacturing & Cost Focus | Requires precise hole size control for component fit. Cost driver: Drilling larger holes and ensuring plating integrity for mechanical strength. | Focus on plating reliability for conductivity. Cost driver: Laser drilling for microvias/HDI, additional lamination steps for blind/buried vias. | Optimize for function. For pure routing, use the smallest reliable via. For components, use a properly sized PTH. Jerico’s free DFM check flags this common error. |
| Thermal & Current Role | Can conduct significant current/heat via the component lead itself. The PTH barrel provides additional thermal mass. | Primary thermal management tool (thermal vias). Current capacity is limited by thin barrel plating unless specifically designed (e.g., filled vias). | For heat sinking, arrays of thermal vias under a pad are more effective than a single PTH. For high current, specialized filled vias or multiple parallel vias are required. |
Why Getting It Wrong Costs You: Real-World Scenarios
- Scenario 1 (Reliability Failure): A designer uses a standard via to mount a header pin. During wave soldering, solder wicks down the via barrel, leaving a void in the joint. Vibration in the field causes the brittle joint to crack. Root Cause: Via used as PTH.
- Scenario 2 (Cost & Performance Impact): To be “safe,” a designer uses 0.8mm PTHs for all layer transitions on a 16-layer digital board. This consumes 30% more routing area, forcing a switch from an 8-layer to a 10-layer stackup, increasing board cost by 25% and adding unnecessary parasitic inductance to high-speed lines. Root Cause: PTH overuse where vias were appropriate.
Advanced Via Technologies: Solving High-Current, Thermal, and HDI Challenges
Once the basic PTH/via distinction is mastered, the next level is selecting and specifying the right type of via for your electrical and thermal needs. Standard through-vias are often insufficient for advanced applications.
1. The High-Current & Thermal Solution: Filled and Plugged Vias
In power electronics (EV chargers, motor drives) and high-power LED applications, standard via barrels are bottleneck for current and heat. A via with a 0.3mm diameter and 25μm copper wall has a DC resistance of several milliohms and limited thermal mass.
Jerico’s Engineered Solution: We offer via filling and copper plugging as a core capability, often integrated with our Heavy Copper PCB technology.
- Thermally Conductive Epoxy Fill: Vias under power components are filled with a special epoxy. This 1) prevents solder wicking during assembly, 2) provides a direct thermal path to inner planes or the opposite side, and 3) adds mechanical support.
- Copper-Plugged Vias (VIPPO): For the ultimate in current carrying and thermal conductivity, vias are completely electroplated shut with copper. This creates a solid copper pillar through the board, reducing resistance by over 50% and acting as a superb thermal column. This process is critical for IPC Class 3 and IATF 16949 compliant automotive boards where long-term thermal cycling reliability is non-negotiable.
Performance Data: For a 0.3mm via in a 1.6mm board carrying 5A DC:
• Standard Via: ~4.2 mΩ resistance, ~0.8°C/W thermal resistance.
• Copper-Plugged Via: ~1.8 mΩ resistance, ~0.3°C/W thermal resistance.
This translates to ~60% lower power loss and ~60% better heat transfer, allowing higher power density or increased reliability.
2. The HDI & Signal Integrity Solution: Microvias and Blind/Buried Vias
For high-speed digital designs (server motherboards, FPGA boards) and space-constrained devices (smartphones, wearables), traditional through-vias are a major obstacle. They pierce all layers, creating long parasitic “stubs” that act as antennas, reflecting signals and degrading integrity at multi-gigabit rates.
Jerico’s HDI Expertise: Our HDI PCB manufacturing utilizes laser-drilled microvias and sequential lamination to build precise interconnects.
- Microvias (⌀ ≤ 0.15mm): Drilled by laser, these connect only two adjacent layers (e.g., L1-L2 or L2-L3). They eliminate stubs entirely, drastically reducing parasitic capacitance and inductance.
- Blind and Buried Vias: Blind vias connect an outer layer to an inner layer but do not go through the entire board. Buried vias connect inner layers only. These structures, built through sequential lamination, free up 100% of the routing area on layers they don’t connect to, enabling higher component density.
Signal Integrity Impact: Replacing a through-via in a 10-layer, 100-ohm differential pair with a stub-less microvia/blind via combination can improve insertion loss by 0.5-1.0 dB at 10 GHz and significantly reduce unwanted resonance, enabling cleaner data transmission for protocols like PCIe 5.0 or 112G SerDes.
The Jerico Advantage: From Design Review to Certified Reliability
Specifying the right via technology is futile if your manufacturer cannot execute it with precision and repeatability. Jerico bridges the gap between design intent and manufactured reality.
Factory-Direct DFM Partnership
As a factory-direct manufacturer, our engineers review your design before tooling. We don’t just check rules; we provide actionable feedback:
- “Your 0.2mm via in the 2.4mm power plane has an 12:1 aspect ratio. For reliable copper plating per IPC-6012, we recommend increasing hole size to 0.25mm or using a via-in-pad with fill.”
- “The thermal via array under the QFN can be optimized from a 3×3 grid of standard vias to a 2×2 grid of copper-plugged vias for equivalent performance, saving space.”
Certified Process, Guaranteed Reliability
Our IATF 16949 and IPC Class 3 commitments are applied directly to via formation:
- Plating Thickness Control: We ensure via barrel copper meets or exceeds IPC Class 3 requirements (typically ≥20μm), verified by cross-sectioning.
- Material Compatibility: For high-frequency or ceramic-based boards, we use compatible fill materials and processes that account for coefficient of thermal expansion (CTE) mismatch, preventing via barrel cracking.
- No MOQ, Rapid Prototyping: Test your advanced via strategies with our 1-piece order and 24-hour quick-turn services. Validate performance before committing to volume.
Optimize Your Via Strategy with a Free DFM Analysis
Don’t let via design be an afterthought. Submit your design files for a comprehensive review by Jerico’s engineering team. Receive a detailed report on current capacity, thermal performance, and manufacturability of every critical via and PTH in your design.
Upload Your Gerber for a Free Via DFM CheckVia & PTH Design: Expert FAQ
A simple rule of thumb is inadequate for high-current designs. The current capacity depends on:
- Cross-sectional area of the copper barrel: I_max ∝ (π * d * t), where d is finished hole diameter, t is plating thickness.
- Allowable temperature rise: A common standard is a 10°C rise. The via’s thermal resistance to the planes/ambient is key.
- Number of vias in parallel: For a 5A current, using 2-3 standard vias in parallel is often safer and more reliable than one large via.
Both techniques aim to remove the unused via stub for signal integrity, but they differ fundamentally:
- Blind/Buried Vias (HDI): Built during sequential lamination, they physically do not create a stub. This is the cleanest, highest-performance solution but adds cost and complexity. Ideal for very high-density interconnect (HDI) designs and the highest speed signals (>25 Gbps).
- Backdrilling: A secondary drilling operation removes the conductive stub from a standard through-via after plating. It’s a cost-effective alternative for thicker, lower-layer-count boards where HDI is not otherwise needed. However, it leaves a non-conductive air gap in the hole, which can trap contaminants and is not acceptable for all reliability standards (e.g., some automotive applications).
Adherence to IPC standards is the baseline for reliability. Key standards include:
- IPC-6012: Qualification and Performance Specification for Rigid Printed Boards. Defines acceptability for plating thickness (e.g., Class 3 requires minimum 20μm in hole), voids, and hole wall integrity. This is the overarching quality spec.
- IPC-A-600: Acceptability of Printed Boards. The visual counterpart to IPC-6012, with images defining acceptable vs. defective conditions for vias and PTHs (e.g., plating nodules, cracks, roughness).
- IPC-4761: Design Guide for Protection of Printed Board Via Structures. Covers via tenting, filling, and plugging methods to protect against contamination and solder wicking.
- IPC-7093: Design and Assembly Process Implementation for BGAs. Contains vital information on via-in-pad design, which is critical for modern components and often requires filled microvias.
